Advanced Encryption Standard (AES) is one of the most common standard encryption algorithms. Inspired by its characteristics, AES algorithm can be implemented on various HARDWARE PLATFORMS such as FPGA. Also, the data path can be implemented in either loop-unrolling or rolling architecture. These two architectures have direct impact on the amount of area consumption on the chip as well as system throughput. Then, a smart design should be able to consider the trade-off between area and throughput and provide a good balance between these two conflicting factors. In this paper, we propose such a design to represent the area-throughput trade-off for FPGA implementation of the AES algorithm. With loop unrolling and pipelining techniques, throughput of 71.35 Gbps is achievable in Virtex 7 FPGA (xc7v585t-3ff1157). This design has just used 3669 Slices on the chip. The extracted results from the Place & Route report of Xilinx ISE 14.2 indicates that the maximum attainable clock frequency is 570.776 MHz.

There are many methods for RNS implementation. The Bajard method is the fastest RNS implementation until now. One of the goals of this paper is to optimize this method to achieve higher performance for HARDWARE implementation of RSA cryptosystem. Higher performance means increase in processing speed and less area. Proper HARDWARE architectures for this method are proposed. For this purpose the number of multiplications is the criterion of the processing speed and the required memory for saving the constant values indicates the area required for this system. The number of multiplications is reduced by 400/(3k+ 11) percent (k is the number of modulus) in the final improved system and the number of constant values reduced by 50 percent.

Microarray technology is a new and powerful tool for concurrent monitoring of large number of genes expressions. Each microarray experiment produces hundreds of images. Each digital image requires a large storage space. Hence, real-time processing of these images and transmission of them necessitates efficient and custom-made lossless compression schemes. In this paper, we offer a new architecture for lossless compression of microarray images. In this architecture, we have used a dedicated HARDWARE for separation of foreground pixels from the background ones. By separating these pixels and using pipeline architecture, a higher lossless compression ratio has been achieved as compared to other existing methods.

Attitude dynamics simulators are one of the most common facilities utilized in spacecraft attitude and stability researches, because these systems produce a free and unconstrained rotational motion. Therefore, they (spacecraft attitude dynamics simulators) provide a platform to perform practical tests on satellite or spacecraft in easy way. Simulation of space environment (such as frictionless, torque free and unconstrained motion) is the best specification of such devices that help scientists (or specialists, students and space users) to have constrained or unconstrained PLATFORMS for three (3) degrees of freedom motions. This paper (article) intends to present a novel classification of satellite (spacecraft) simulators in first phase (level) and then tries to focus on air-bearing-based simulators and presents a survey of them (spacecraft attitude dynamics simulators). Investigation of available sample of satellite simulators and verification of them are the other specifications of this article caused to be a good reference for students and researchers.